Reliability of hardware is highly dependent upon the extent of random access memory (RAM) testing that is performed before shipping the product. In order to provide maximum coverage for external memory attached to application specific integrated circuits (ASIC) as well as ASIC internal memories, previous wide area network (WAN) switches have relied on the use of the embedded processor to test each RAM and each memory location. The quality of RAM test coverage goes up with each location tested and with multiple data patterns per location. This conventional approach is very time consuming because the processor has to synchronously execute the diagnostic program that requires several instructions and memory fetches per address location tested. The length of time used to completely test a board is exacerbated by the cost of the test fixture environment. The advent of large asynchronous transfer mode (ATM) switches compounds the problem with the switch's vast array of internal and external memories.